Various types of compound semiconductor device that contains a compound semiconductor, such as SiC and GaN, have been conventionally proposed. These compound semiconductor devices include a vertical switching element, such as a vertical metal-oxide-semiconductor field-effect transistor (MOSFET) having an inverted type trench gate structure.
For example, the vertical MOSFET having the inverted type trench gate structure causes such an action that applies a gate voltage to a gate electrode inside a trench to form a channel in a p-type base area located on a trench side face, and produces an electrical current flowing between a drain and a source via the channel thus formed.
Patent Literature 1 describes a vertical MOSFET configured as above and having a structure capable of implementing measures for securing inductive load resistance. More specifically, for manufacturing this structure, a deep p-type layer that reaches deeper than a p-type base area is formed. Avalanche breakdown is caused preferentially on a bottom face of the deep p-type layer. Surge energy is extractable in this state along a route where a parasitic transistor is difficult to operate. Accordingly, sufficient inductive load resistance is obtainable. In case of a deep p-type layer extending deep, however, an n−-type drift layer at a junction field effect transistor (JFET) is depleted by the presence of a depletion layer extending from the deep p-type layer toward a drift layer. In this condition, JFET resistance increases. According to Patent Literature 1, therefore, an n-type limiting layer is provided at a side face position of the deep p-type layer other than the bottom face side thereof to limit an extension amount of the depletion layer extending from the side face of the deep p-type layer, and thereby reduce a rise of JFET resistance.